Silicon Validation position at AxiusTek in Santa Clara

AxiusTek is at the momment seeking for Silicon Validation on Sat, 16 Nov 2013 17:01:44 GMT. Pre-Silicon Validation Location- Santa Clara, CA W2 Full time Number of position â€" 1 Job Description Verification Architect with at least 8 years of experience in IP and SoC RTL Verification. Work with a team to create and enhance a SystemVerilogOVM validation testbench and associated design automation tools and methodologies. Responsibilities include Creating SystemVerilogOVM testbench... Read more »