Engineer, Staff Verification occupation at Marvell in Santa Clara

Marvell is currently interviewing Engineer, Staff Verification on Sat, 27 Jul 2013 03:35:42 GMT. • BS/MS/PHD EE, or CE. • 8+ years of design verification experience with advance verification methodology such as System Verilog, SVA, UMM and/or OVM • Strong working knowledge of UNIX environment and Revision Control tools. • Excellent debug skills with simulation testbenches. • Familiarity with system architecture, memory organization hardware architecture, and bus protocols such as USB, AXI, PCIE... Read more »