Engineer, Design Verification Test (DVT) vacancy at Marvell in Santa Clara

Marvell is in need of Engineer, Design Verification Test (DVT) on Mon, 03 Jun 2013 20:41:34 GMT. - Hands on DFT experience including boundary scan, memory BIST, scan, BIST, 3rd party IP integration, at-speed and IDDQ tests, ATPG, and fault simulation. - Experience with ATE pattern bringup and volume production preferred. - Expertise with DFT tools from Synopsys, Mentor Graphics, Syntest, and Logic Vision. - Strong logic Design and verification background with experience in STA. - Proficient in... Read more »